./cad/abc [system for sequential logic synthesis and verification]
[+] Add this package to your ports tracker

[ CVSweb ] [ Homepage ] [ RSS feed ]

Version: 1.01.20180722, Package name: abc-1.01.20180722
Maintained by: Alessandro De Laurenzis
Master sites:
Description
ABC is a growing software system for synthesis and verification of binary
sequential logic circuits appearing in synchronous hardware designs. ABC
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
optimal-delay DAG-based technology mapping for look-up tables and standard
cells, and innovative algorithms for sequential synthesis and verification.


Filesize: 5520.949 KB
Version History (View Complete History)
  • (2018-08-08) Package added to openports.se, version abc-1.01.20180722 (created)
[show/hide] View available PLISTS (Can be a lot of data)