./cad/opensta [Parallax Static Timing Analyzer]
[+] Add this package to your ports tracker

[ CVSweb ] [ Homepage ] [ RSS feed ]

Version: 2.0.12.20190329, Package name: opensta-2.0.12.20190329
Maintained by: Alessandro De Laurenzis
Master sites:
Description
OpenSTA is a gate level static timing verifier. As a stand-alone
executable it can be used to verify the timing of a design using
standard file formats:
- Verilog netlist
- Liberty library
- SDC timing constraints
- SDF delay annotation
- SPEF parasitics

OpenSTA uses a TCL command interpreter to read the design, specify
timing constraints and print timing reports.


Filesize: 889.696 KB
Version History (View Complete History)
  • (2019-03-30) Updated to version: opensta-2.0.12.20190329
  • (2019-03-27) Package added to openports.se, version opensta-2.0.11.20190327 (created)
[show/hide] View available PLISTS (Can be a lot of data)