./lang/verilator [very fast free Verilog HDL simulator]
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Version: 3.912, Package name: verilator-3.912
Maintained by: The OpenBSD ports mailing-list
Master sites:
Description
Verilator is the fastest free Verilog HDL simulator, and beats most
commercial simulators. It compiles synthesizable Verilog (not test-bench
code!), plus some PSL, SystemVerilog and Synthesis assertions into C++
or SystemC code. It is designed for large projects where fast simulation
performance is of primary concern, and is especially well suited to
generate executable models of CPUs for embedded software design teams.


Filesize: 2004.501 KB
Version History (View Complete History)
  • (2017-10-06) Updated to version: verilator-3.912
  • (2017-02-13) Updated to version: verilator-3.900
  • (2014-05-21) Updated to version: verilator-3.860
  • (2013-05-23) Updated to version: verilator-3.847
  • (2013-05-14) Updated to version: verilator-3.846
  • (2013-01-16) Updated to version: verilator-3.844
  • (2011-11-13) Package added to openports.se, version verilator-3.824 (created)
[show/hide] View available PLISTS (Can be a lot of data)

CVS Commit History:

   2017-07-26 16:45:35 by Stuart Henderson | Files touched by this commit (937)
Log message:
bump LIBCXX/LIBECXX/COMPILER_LIBCXX ports.
   2017-07-23 03:26:30 by Marc Espie | Files touched by this commit (244)
Log message:
add pthread to COMPILER_LIBCXX.
white lie, but it allows clang and gcc to be more similar
bump accordingly.
   2017-07-16 13:19:06 by Marc Espie | Files touched by this commit (880)
Log message:
use COMPILER_LIBCXX where applicable
   2017-04-10 05:46:23 by Stuart Henderson | Files touched by this commit (276)
Log message:
use LIBCXX
   2017-02-13 03:27:00 by Benoit Lecocq | Files touched by this commit (3)
Log message:
Update to verilator-3.900.
   2017-02-13 03:27:00 by Benoit Lecocq | Files touched by this commit (3)
Log message:
Update to verilator-3.900.
   2017-02-13 03:27:00 by Benoit Lecocq | Files touched by this commit (3)
Log message:
Update to verilator-3.900.