./cad/qflow [full end-to-end digital synthesis flow for VLSI ASIC designs]
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Version: 1.4.83, Package name: qflow-1.4.83
Maintained by: Alessandro De Laurenzis
Master sites:
A digital synthesis flow is a set of tools and methods used to turn a
VLSI design written in a high-level behavioral language like Verilog
or VHDL into a physical circuit, which can either be configuration code
for an FPGA target or a layout in a specific technology, that would
become part of an IC.
Qflow uses a complete and open source tool chain for synthesizing
digital circuits starting from Verilog source and ending in physical
layout for a specific target fabrication process.

Filesize: 930.38 KB
Version History (View Complete History)
  • (2020-07-03) Package added to openports.se, version qflow-1.4.83 (created)
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