./cad/qflow [full end-to-end digital synthesis flow for VLSI ASIC designs]
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Version: 1.4.83, Package name: qflow-1.4.83
Maintained by: Alessandro De Laurenzis
Master sites:
Description
A digital synthesis flow is a set of tools and methods used to turn a
VLSI design written in a high-level behavioral language like Verilog
or VHDL into a physical circuit, which can either be configuration code
for an FPGA target or a layout in a specific technology, that would
become part of an IC.
Qflow uses a complete and open source tool chain for synthesizing
digital circuits starting from Verilog source and ending in physical
layout for a specific target fabrication process.

Filesize: 930.38 KB
Version History (View Complete History)
  • (2020-07-03) Package added to openports.se, version qflow-1.4.83 (created)
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CVS Commit History:

   2021-02-23 12:39:53 by Stuart Henderson | Files touched by this commit (743)
Log message:
Reverse the polarity of MODPY_VERSION; default is now 3.x,
if a port needs 2.x then set MODPY_VERSION=${MODPY_DEFAULT_VERSION_2}.
This commit doesn't change any versions currently used; it may be that
some ports have MODPY_DEFAULT_VERSION_2 but don't require it, those
should be cleaned up in the course of updating ports where possible.
Python module ports providing py3-* packages should still use
FLAVOR=python3 so that we don't have a mixture of dependencies some
using ${MODPY_FLAVOR} and others not.