./cad/yosys [framework for Verilog RTL synthesis]
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Version: 0.9, Package name: yosys-0.9
Maintained by: Alessandro De Laurenzis
Master sites:
Description
Yosys Open SYnthesis Suite

Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains. Selected features and typical applications:

- Process almost any synthesizable Verilog-2005 design
- Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
- Built-in formal methods for checking properties and equivalence
- Mapping to ASIC standard cell libraries (in Liberty File Format)
- Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
- Foundation and/or front-end for custom flows

Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the Yosys C++ code base.


Filesize: 1269.087 KB
Version History (View Complete History)
  • (2019-10-28) Updated to version: yosys-0.9
  • (2019-01-09) Updated to version: yosys-0.8
  • (2018-08-11) Package added to openports.se, version yosys-0.7 (created)
[show/hide] View available PLISTS (Can be a lot of data)

CVS Commit History:

   2020-04-12 08:46:04 by Stuart Henderson | Files touched by this commit (5)
Log message:
update maintainer email, from Alessandro De Laurenzis
   2019-10-28 02:00:17 by Anthony J. Bentley | Files touched by this commit (3)
Log message:
Update to yosys-0.9.
Release notes:
https://github.com/YosysHQ/yosys/releases/tag/yosys-0.9
   2019-07-12 14:44:13 by Stuart Henderson | Files touched by this commit (877)
Log message:
replace simple PERMIT_PACKAGE_CDROM=Yes with PERMIT_PACKAGE=Yes
   2019-04-30 01:21:58 by Anthony J. Bentley | Files touched by this commit (2)
Log message:
Enable "show" functionality.
From Alessandro De Laurenzis (maintainer); thanks!
   2019-04-28 16:35:40 by Christian Weisgerber | Files touched by this commit (2)
Log message:
drop workaround for gcc4.9 that is no longer needed for gcc8
   2019-04-28 14:52:03 by Stuart Henderson | Files touched by this commit (715)
Log message:
bump all the py3 things, _SYSTEM_VERSION didn't quite work out how
we expected and it's easier|safer to do it this way than fiddle with
pkg_add now. thanks aja for update tests with a quick bulk.
   2019-01-08 21:27:10 by Anthony J. Bentley | Files touched by this commit (6)
Log message:
Update to yosys-0.8.
Release notes: https://github.com/YosysHQ/yosys/releases/tag/yosys-0.8
ok Alessandro De Laurenzis (maintainer)
   2018-11-18 13:43:23 by Christian Weisgerber | Files touched by this commit (1)
Log message:
ports-gcc 4.9 requires explicit -std=c++11